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rev. 0.2 2/11 copyright ? 2011 by silicon laboratories si824x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si824x c lass d a udio d river with p recision d ead -t ime g enerator features applications description the si824x isolated driver family co mbines two isolated drivers in a single package. the SI8241/44 are high-side/low-s ide drivers specifically targeted at high-power (>30 w) audio applications. ve rsions with peak output currents of 0.5 a (SI8241) and 4.0 a (si8244) are available. all drivers operate with a maximum supply voltage of 24 v. based on silicon labs' proprietary isolat ion technology, the si824x audio drivers incorporate input-to-output and output-to- output isolation, which enables level- translation of signals without additional extern al circuits as well as use of bipolar supply voltage up to 750 v. the si824x audio drivers feature an integrated dead- time generator that provides highly pr ecise control for achieving optimal thd. these products also have overlap prot ection that safeguar ds against shoot- through current damage. the cmos-based design also provides robust immunity from latch-up and high-voltage transients. the extremely low propagation delays enable faster modulation frequencies for an enhanced audio experience. the ttl level compatible inputs with >400 mv hysteresis are available in pwm input configuration; other options include uvlo levels of 8 v or 10 v. these products are available in narrow body soic packages. functional block diagram ? 0.5 a peak output (SI8241) ? 4.0 a peak output (si8244) ? pwm input ? high-precision linear programmable dead-time generator ?? 0.4ns to 1s ? high latchup immunity >100 v/ns ? up to 1500 vrms output-output isolation, supply voltage of 750 v ? input to output isolation for low noise (up to 2500 v) ? up to 8 mhz operation ? wide operating range ?? ?40 to +125 c ? transient immunity >45 kv/s ? rohs-compliant ?? soic-16 narrow body ? class d audio amplifiers gndi vddi pwm vdda voa gnda vob vddb gndb disable dt uvlo isolation isolation programmable dead time, control gating SI8241/44 patents pending ordering information: see page 25. pin assignments pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc vddb vob gndb SI8241/44 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 nc free datasheet http:///
si824x 2 rev. 0.2 free datasheet http:///
si824x rev. 0.2 3 t able of c ontents section page 1. top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1. typical performance characterist ics (0.5 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. typical performance characterist ics (4.0 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. family overview and logic operation during star tup . . . . . . . . . . . . . . . . . . . . . . . 17 3.4. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.6. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7. undervoltage locko ut operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8. programmable dead time and overlap protection . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1. class d digital audio driv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8. land pattern: 16-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. top marking: 16-pin na rrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 free datasheet http:///
si824x 4 rev. 0.2 1. top-level block diagram figure 1. SI8241/44 single-input high-side/low-side isolated drivers SI8241/44 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt lpwm lpwm free datasheet http:///
si824x rev. 0.2 5 2. electrical specifications table 1. electrical characteristics 1 4.5 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units dc specifications input-side power supply voltage vddi 4.5 ? 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb (see ?6. ordering guide? ) 6.5 ? 24 v input supply quiescent current iddi(q) SI8241/44 ? 2 3 ma output supply quiescent current idda(q), iddb(q) current per channel ? ? 3.0 ma input supply active current iddi pwm freq = 500 khz ? 2.5 ? ma output supply active current iddo pwm freq = 500 khz ? 3.6 ? ma input pin leakage current ipwm ?10 ? +10 a dc input pin leakage current idisable ?10 ? +10 a dc logic high input threshold vih 2.0 ? ? v logic low input threshold vil ? ? 0.8 v input hysteresis vi hyst 400 450 ? mv logic high output voltage voah, vobh ioa, iob = ?1 ma (vdda /vddb) ? 0.04 ?? v logic low output voltage voal, vobl ioa, iob = 1 ma ? ? 0.04 v output short-circuit pulsed sink current ioa(scl), iob(scl) SI8241, figure 2 ? 0.5 ? a si8244, figure 2 ? 4.0 ? a output short-circuit pulsed source current ioa(sch), iob(sch) SI8241, figure 3 ? 0.25 ? a si8244, figure 3 ? 2.0 ? a output sink resistance r on(sink) SI8241 ? 5.0 ? ? si8244 ? 1.0 ? ? output source resistance r on(source) SI8241 ? 15 ? ? si8244 ? 2.7 ? ? notes: 1. vdda = vddb = 12 v for 8 v uvlo and 10 v uvlo devices. 2. the largest rdt resistor that can be used is 220 k ? . free datasheet http:///
si824x 6 rev. 0.2 vddi undervoltage threshold vddi uv+ vddi rising 3.60 4.0 4.45 v vddi undervoltage threshold vddi uv? vddi falling 3.30 3.70 4.15 v vddi lockout hysteresis vddi hys ?250?mv vdda, vddb undervoltage threshold vdda uv+ , vddb uv+ vdda, vddb rising 8v threshold see figure 34 on page 21. 7.50 8.60 9.40 v 10 v threshold see figure 35 on page 21. 9.60 11.1 12.2 v vdda, vddb undervoltage threshold vdda uv? , vddb uv? vdda, vddb falling 8v threshold see figure 34 on page 21. 7.20 8.10 8.70 v 10 v threshold see figure 35 on page 21. 9.40 10.1 10.9 v vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 8 v ? 600 ? mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 10 v ? 1000 ? mv ac specifications minimum pulse width ? 10 ? ns propagation delay t phl , t plh cl = 1 nf ? 25 60 ns pulse width distortion |t plh - t phl | pwd ? 1.0 5.60 ns programmed dead time 2 dt see figures 36 and 37 0.4 ? 1000 ns output rise and fall time t r ,t f c l = 1 nf (SI8241) ? ? 20 ns c l = 1 nf (si8244) ? ? 12 ns shutdown time from disable true t sd ??60 ns restart time from disable false t restart ??60 ns device start-up time t start time from vdd_ = vdd_uv+ to voa, vob = via, vib ?57s common mode transient immunity cmti via, vib, pwm = vddi or 0 v 25 45 ? kv/s table 1. electrical characteristics 1 (continued) 4.5 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units notes: 1. vdda = vddb = 12 v for 8 v uvlo and 10 v uvlo devices. 2. the largest rdt resistor that can be used is 220 k ? . free datasheet http:///
si824x rev. 0.2 7 2.1. test circuits figures 2 and 3 depict sink current and source current test circuits. figure 2. sink current test circuit figure 3. source current test circuit input 1 f 100 f 10 rsns 0.1 si824x 1 f cer 10 f el vdda = vddb = 15 v in_ out_ vss vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi (5 v) 5 v + _ input 1 f 100 f 10 rsns 0.1 si824x 1 f cer 10 f el vdda = vddb = 15 v in_ out_ vss vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi (5 v) 5 v + _ free datasheet http:///
si824x 8 rev. 0.2 table 2. absolute maximum ratings 1 parameter symbol min typ max units storage temperature 2 t stg ?65 ? +150 c ambient temperature under bias t a ?40 ? +125 c input-side supply voltage vddi ?0.6 ? 6.0 v driver-side supply voltage vdda, vddb ?0.6 ? 30 v voltage on any pin with respect to ground vin ?0.5 ? vdd + 0.5 v output drive current per channel i o ?? 10 ma lead solder temperature (10 sec) ? ? 260 c latchup immunity 3 ?? 100 v/ns maximum isolation (input to output) ? ? 2500 v rms maximum isolation (output to output) ? ? 1500 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. vde certifies storage temperature from ?40 to 150 c. 3. latchup immunity specification is for slew rate applied across gndi and gnda or gndb. table 3. regulatory information* csa the si824x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 300 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 300 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. vde the si824x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 560 v peak for basic insulation working voltage. ul the si824x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 2500 v rms isolation voltage for basic protection. *note: regulatory certifications apply to 2.5 kv rms rated devices, which are production tested to 3.0 kv rms for 1 sec. for more information, see "6.ordering guide" on page 25. free datasheet http:///
si824x rev. 0.2 9 table 4. insulation and safety-related specifications parameter symbol test condition value unit nbsoic-16 2.5 kv rms nominal air gap (clearance) 1 l(1o1) 4.01 mm nominal external tracking (creepage) 1 l(1o2) 4.01 mm minimum internal gap (internal clearance) 0.011 mm tracking resistance (proof tracking index) pti iec60112 600 v erosion depth ed 0.019 mm resistance (input-output) 2 r io 10 12 ? capacitance (input-output) 2 c io f=1mhz 1.4 pf input capacitance 3 c i 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in ?7. package outline: 16-pin narrow body soic? . vde certifies the clearance and creepage limits as 4.7 mm mi nimum for the nb soic-16. ul does not impose a clearance and creepage minimum for co mponent level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic 16. 2. to determine resistance and capacitance, the si824x is converted into a 2-terminal dev ice. pins 1?8 are shorted together to form the first terminal and pi ns 9?16 are shorted together to form th e second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 5. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification nb soic-16 basic isolation group material group i installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii rated mains voltages < 600 v rms i-ii free datasheet http:///
si824x 10 rev. 0.2 table 6. iec 60747-5-2 insulation characteristics* parameter symbol test condition characteristic unit nb soic-16 maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1050 v peak transient overvoltage v iotm t = 60 sec 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si824x provides a climate classification of 40/125/21. table 7. iec safety limiting values 1 parameter symbol test co ndition nb soic-16 unit case temperature t s 150 c safety input current i s ? ja = 105 c/w (nb soic-16), v ddi =5.5v, v dda =v ddb =24v, t j = 150 c, t a =25c 50 ma device power dissipation 2 p d 1.2 w notes: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figure 4. 2. the si82xx is tested with v ddi =5.5v, v dda =v ddb =24v, t j =150oc, c l = 100 pf, input 2 mhz 50% duty cycle square wave. free datasheet http:///
si824x rev. 0.2 11 figure 4. nb soic-16, thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 8. thermal characteristics parameter symbol nb soic-16 unit ic junction-to-air thermal resistance ? ja 105 c/w 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vddi = 5.5 v vdda, vddb = 24 v 10 30 50 free datasheet http:///
si824x 12 rev. 0.2 3. functional description the operation of an si824x channel is analogous to that of an opto coupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si824x channel is shown in figure 5. figure 5. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 6 for more details. figure 6. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver dead time generator 0.5 to 4 a peak gnd v dd driver input signal output signal modulation signal free datasheet http:///
si824x rev. 0.2 13 3.1. typical performan ce characteristics (0.5 amp) the typical performance characteristics depicted in figure s 7 through 18 are for information purposes only. refer to table 1 on page 5 for actual specification limits. figure 7. rise/fall time vs. supply voltage figure 8. propagation delay vs. supply voltage figure 9. supply current vs. supply voltage figure 10. supply current vs. supply voltage figure 11. supply current vs. temperature figure 12. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 1 1.5 2 2.5 3 3.5 4 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 1 2 3 4 5 6 7 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 1 2 3 4 5 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise free datasheet http:///
si824x 14 rev. 0.2 figure 13. propagation delay vs. load figure 14. propagation delay vs. temperature figure 15. output sink current vs. supply voltage figure 16. output source current vs. supply voltage figure 17. output sink current vs. temperature figure 18. output source current vs. temperature 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h 4 5 6 7 8 9 10 12 14 16 18 20 22 24 sink current (a) supply voltage (v) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 10 15 20 25 source current (a) supply voltage (v) vdd=12v, vout=vdd-5v 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -40 -10 20 50 80 110 sink current (a) temperature ( c) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 -40 -10 20 50 80 110 source current (a) temperature ( c) vdd=12v, vout=vdd-5v free datasheet http:///
si824x rev. 0.2 15 3.2. typical performan ce characteristics (4.0 amp) the typical performance characteristics depicted in figures 19 through 30 are for information purposes only. refer to table 1 on page 5 for actual specification limits. figure 19. rise/fall time vs. supply voltage figure 20. propagation delay vs. supply voltage figure 21. supply current vs. supply voltage figure 22. supply current vs. supply voltage figure 23. supply current vs. temperature figure 24. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 0 2 4 6 8 10 12 14 9141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 12 14 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 012345678910 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise free datasheet http:///
si824x 16 rev. 0.2 figure 25. propagation delay vs. load figure 26. propagation delay vs. temperature figure 27. output sink current vs. supply voltage figure 28. output source current vs. supply voltage figure 29. output sink current vs. temperature figure 30. output source current vs. temperature 10 15 20 25 30 35 40 45 50 012345678910 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h 4 5 6 7 8 9 10 12 14 16 18 20 22 24 sink current (a) supply voltage (v) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 10 15 20 25 source current (a) supply voltage (v) vdd=12v, vout=vdd-5v 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -40 -10 20 50 80 110 sink current (a) temperature ( c) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 -40 -10 20 50 80 110 source current (a) temperature ( c) vdd=12v, vout=vdd-5v free datasheet http:///
si824x rev. 0.2 17 3.3. family over view and logic operation during startup the si824x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 3.3.1. products table 9 shows the configuration and functional overview for each product in this family. 3.3.2. device behavior table 10 contains truth tables for the SI8241/4 families. table 9. si824x family overview part number configuration uvlo voltage programmable dead time inputs peak output current (a) SI8241 high-side/low-side 8 v/10 v ? pwm 0.5 si8244 high-side/low-side 8 v/10 v ? pwm 4.0 table 10. si824x family truth table* SI8241/4 (pwm input high-si de/low-side) truth table pwm input vddi state disable output notes voa vob h powered l h l output transition occurs after internal dead time expires. l powered l l h output transition occurs after internal dead time expires. x unpowered x l l output returns to input state within 7 s of vddi power restoration. x powered h l l device is disabled. *note: this truth table assumes vdda and vddb are powered. if vdda and vddb are below uvlo, see "3.7.2.undervoltage lockout" on page 20 for more information. free datasheet http:///
si824x 18 rev. 0.2 3.4. power supply connections isolation requirements mandate individual supplies fo r vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pi ns of the si824x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 3.5. power dissipation considerations proper system design must assure that the si824x operates within safe therma l limits across the entire load range. the si824x total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load. equation 1 show s total si824x power dissipation. in a non-overlapping system, such as a high-side/low-side driver, n = 1. equation 1. the maximum power dissipation allowable for the si824x is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2: equation 2. substituting values for p dmax t jmax , t a , and ? ja into equation 2 results in a maximum allowable total power dissipation of 1.19 w. maximum allowable load is found by substituting this limit and the appropriate datasheet values from table 1 on page 5 into equation 1 and si mplifying. the result is equation 3 (0.5 a driver) and equation 4 (4.0 a driver), both of which assume vddi = 5 v and vdda = vddb = 18 v. equation 3. equation 4. p d v ddi i ddi 2v ddo i qout c int v ddo 2 f + ?? 2n c l v ddo 2 f ?? ++ where: p d is the total si824x device power dissipation (w) i ddi is the input-side maximum bias current (3 ma) i qout is the driver die maximum bias current (2.5 ma) c int is the internal parasitic capacitance (75 pf for the 0.5 a driver and 370 pf for the 4.0 a driver) v ddi is the input-side vdd supply voltage (4.5 to 5.5 v) v ddo is the driver-side supply voltage (10 to 24 v) f is the switching frequency (hz) n is the overlap constant (max value = 2) = p dmax t jmax t a ? ? ja --------------------------- where: p dmax = maximum si824x power dissipation (w) t jmax = si824x maximum junction temperature (150 c) t a = ambient temperature (c) ? ja = si824x junction-to-air thermal resistance (105 c/w) f = si824x switching frequency (hz) ? c l(max) 1.4 10 3 ? ? f -------------------------- 7.5 ? 10 11 ? ? = c l(max) 1.4 10 3 ? ? f -------------------------- 3.7 ? 10 10 ? ? = free datasheet http:///
si824x rev. 0.2 19 equation 1 and equation 2 are graphed in figure 31 where the points along the load line represent the package dissipation-limited value of cl for the corresponding switching frequency. figure 31. max load vs. switching frequency figure 32. switching frequency vs. load current 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000 100 150 200 250 300 350 400 450 500 550 600 650 700 frequency (khz) max load (pf) 0.5a driver (pf) 4a driver (pf) t a = 25 c 0 5 10 15 20 0 200 400 600 800 1000 vdda supply current (ma) switching frequency (khz) vdd=15v, 25 c c l = 1000pf c l = 500pf c l = 200pf free datasheet http:///
si824x 20 rev. 0.2 3.6. layout considerations it is most important to minimize ringing in the drive path and noise on the si824x vdd lines. care must be taken to minimize parasitic inductance in these pa ths by locating the si824x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this re ason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and vdd planes for power devices and small signal components provides the best overall noise performance. 3.7. undervoltage lockout operation device behavior during start-up, normal operation and shutdown is shown in figure 33, where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power su pply (vddi) is not present. 3.7.1. device startup outputs voa and vob are held low during power-up un til vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. 3.7.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own undervoltage lockout monitors. the si824x input side enters uvlo when vddi < vddi uv? , and exits uvlo when vddi > vddi uv+ . the driver outputs, voa and vob, remain low when the input side of the si824x is in uvlo and their respective vdd supply (vdda, vddb) is within toler ance. each driver output can enter or ex it uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdda uv? and exits uvlo when vdda rises above vdda uv+ . figure 33. device behavior during normal operation and shutdown pwm voa disable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd vdd hys vdd hys free datasheet http:///
si824x rev. 0.2 21 3.7.3. undervoltage lockout (uvlo) the uvlo circuit unconditionally drives vo low when vdd is below the lockout threshol d. referring to figures 34 and 35, upon power up, the si824x is maintained in uvlo until vdd rises above vdd uv+ . during power down, the si824x enters uvlo when vdd falls below the uvlo threshold plus hysteresis (i.e., vdd < vdd uv+ ? vdd hys ). figure 34. si824x uvlo response (8 v) figure 35. si824x uvlo response (10 v) 3.7.4. control inputs pwm inputs are high-true, ttl level-co mpatible logic inputs. voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 3.7.5. disable input when brought high, the disabl e input unconditionally driv es voa and vob low regardle ss of the states of input. device operation terminates within tsd after disable = v ih and resumes within trestart after disable = v il . the disable input has no effect if vddi is below its uvlo level (i.e. voa, vob remain low). the disable input is typically connected to external protec tion circuitry to unconditionally halt driver operation in the event of a fault. 6.0 10.5 v dduv+ (typ) output voltage (v o ) 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 supply voltage (v dd - v ss ) (v) 8.5 10.5 v dduv+ (typ) output voltage (v o ) 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 supply voltage (v dd - v ss ) (v) free datasheet http:///
si824x 22 rev. 0.2 3.8. programmable dead time and overlap protection all high-side/low-side drivers (si8 241/4) include programmable overlap pr otection to prevent outputs voa and vob from being high at the same time . these devices also include programm able dead time, which adds a user- programmable delay between transitions of voa and vob. when enabled, dead time is present on all transitions, even after overlap recovery. the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per equation 5. minimum dead time (approximately 400 ps) can be achieved by connecting the dt pin to vddi. note that dead time accuracy is limited by the resistor?s (r dt ) tolerance and temperature coefficient. see figures 36 and 37 for additional information about dead time operation. equation 5. figure 36. dead time vs.resistance (r dt ) figure 37. dead time vs.temperature dt 10 rdt where: ? dt dead time (ns) and rdt dead time programming resistor (k ?? = = ? 0 100 200 300 400 500 600 700 800 900 1000 0 20 40 60 80 100 dead-time (ns) dead-time resistance (k ) 0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 dead-time (ns) temperature ( c) r dt = 4k r dt = 10k r dt = 3 k r dt = 5k r dt = 6k r dt = 2 k r dt = 1 k r dt =0 free datasheet http:///
si824x rev. 0.2 23 4. applications the following examples illustrate typical circuit configurations using the si824x. 4.1. class d di gital audio driver figures 38 and 39 show the SI8241/4 controlled by a sing le pwm signal. supply can be unipolar (0 to 1500 v) or bipolar ( 750 v). figure 38. si824x in half-bridge audio application figure 39. si824x in half-bridge audio application d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. vob is connected as a conventional low-si de driver. note that the input side of the si824x requires vdd in the range of 4.5 to 5.5 v, while the vdda and vddb output side supplies must be between 6.5 and 24 v with respect to their respective grounds. the boot-strap start up time will depend on the cb cap chosen. vdd2 is usually the same as vddb. also not e that the bypass capacitors on the si824x should be located as close to the chip as possible. moreover, it is recommended that 0.1 and 10 f bypass capacitors be used to reduce high frequency noise and maximize perfor mance. the d1 diode should be a fast-recovery diode; it should be able to withstand the maximum high voltage (e.g. 1500 v) and be low-loss. see ?an486: high-side bootstrap design using si823x isodrivers in power delivery systems? for more details in selecting the bootstrap cap (cb) and diode (d1). SI8241/4 cb gndi vddi pwm vdda voa gnda vob vddi vddb gndb disable dt rdt controller c1 1uf pwmout i/o q1 q2 d1 vddb c3 10uf vdd2 c2 1 f 1500 v max SI8241/4 cb gndi vddi pwm vdda voa gnda vob vddi vddb gndb disable dt rdt controller c1 1uf pwmout i/o q1 q2 d1 vddb c3 10uf vdd2 c2 1 f +750 v max -750 v max free datasheet http:///
si824x 24 rev. 0.2 5. pin descriptions table 11. SI8241/44 pwm input hs/ls isolated driver (soic-16) pin name description 1 pwm pwm input. 2 nc no connection. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 1 ns dead time when con- nected to vddi or left open (see "3.8.progr ammable dead time and overlap protection" on page 22). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc vddb vob gndb SI8241/44 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 nc free datasheet http:///
si824x rev. 0.2 25 6. ordering guide the currently available opns are listed in table 12. table 12. ordering part numbers ordering part number (opn) input type package drive strength output uvlo voltage isolation rating (input to output) SI8241bb-b-is1 pwm nb soic-16 0.5 a high-side/low-side 8v 2.5 kvrms SI8241cb-b-is1 pwm nb soic-16 10 v si8244bb-c-is1 pwm nb soic-16 4a 8v si8244cb-c-is1 pwm nb soic-16 10 v note: all packages are rohs-compliant. moisture sensitivity level is msl3 for narrow-body soic -16 packages with peak reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. tape and reel options are specified by adding an ?r? suffix to the ordering part number. free datasheet http:///
si824x 26 rev. 0.2 7. package outline: 16 -pin narrow body soic figure 40 illustrates the package details for the si824x in a 16-pin narrow-body soic (so-16). table 13 lists the values for the di mensions shown in the illustration. figure 40. 16-pin small outline integrated circuit (soic) package table 13. package diagram dimensions dimension min max dimension min max a ? 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 ? h 0.25 0.50 b0 . 3 1 0 . 5 1 0 8 c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ip c j-std-020 specification for small body components. free datasheet http:///
si824x rev. 0.2 27 8. land pattern: 16-pin narrow body soic figure 41 illustrates the recommended land pattern details for the si824x in a 16-pin narrow-body soic. table 14 lists the values for the dimens ions shown in the illustration. figure 41. 16-pin narrow body soic pcb land pattern table 14. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. free datasheet http:///
si824x 28 rev. 0.2 9. top marking: 1 6-pin narrow body soic figure 42. 16-pin narrow body soic top marking table 15. 16-pin narrow body soic top marking explanations line 1 marking: base part number ordering options see ordering guide for more information. si824 = isodriver product series y = peak output current ? 1=0.5a ? 4=4.0a u = uvlo level ? b=8v; c=10v v = isolation rating ? b=2.5kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. si824yuv yywwtttttt e4 free datasheet http:///
si824x rev. 0.2 29 d ocument c hange l ist revision 0.1 to revision 0.2 ? deleted table 3. ? added tables 3 through 8. ? added figure 4. ? updated common-mode transient immunity specification throughout. free datasheet http:///
si824x 30 rev. 0.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses. free datasheet http:///

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